1. Field of the Invention
The present invention relates generally to systems and methods for quality control of integrated circuits manufactured by a semiconductor manufacturing process and, more particularly, to a system and method for analyzing defects in multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits manufactured using a semiconductor fabrication process.
2. Description of the Prior Art
A standard memory cell typically stores one bit of information by storing one of two levels of electrical charge in its storage cell, namely, full charge or no charge. Newer memory devices, sometimes referred to as multi-level cell devices, can store more than one bit per cell, by storing two or more levels of electrical charge per memory cell.
Traditionally, with standard memory cell analysis, one would analyze the failed memory cells by assigning each cell to be a failed cell or a passed cell (binary mode). An analysis tool then can classify the failed bit cells by a variety of techniques such as displaying the failed bits in a rectangular grid with X and Y coordinates with different coloring schemes, grouping and classifying the failed bits into bitmap “signatures” or “patterns,” aggregating and grouping the fail signatures and/or failed bits into classes of fails, correlating the failed bits with fabrication defects, etc. The occurrence of defects may cause lower yield in the final memory cell product, where yield may be defined as the number of functional memory cell devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving yield is a critical issue in the semiconductor manufacturing industry. Higher yield translates into more devices that may be sold by the manufacturer, and thus greater profits.
Considered in more detail, typically, semiconductor manufacturers collect and analyze data about various defects in memory cell devices. Based on data analysis, they adjust the memory cell device design and/or process steps and/or tool specifications in an attempt to improve the yield of the process. This has created a need for a new generation of tools and techniques for defect analysis for memory cell yield management.
U.S. Pat. No. 6,470,229 B1 assigned to the same assignee as the present application discloses a yield management system and technique to generate a yield model. The system can also accept user input to modify the generated model.
Additionally, a Genesis™ Bitmap Analysis product module is commercially available from the assignee of U.S. Pat. No. 6,470,229 B1 to extend the capabilities of the yield management system to direct bitmap-level analysis of standard memory cells. The Bitmap Analysis product module suite allows a user to graph and analyze bitmap data. Bit failures are revealed to the user visually with interactive bitmaps. Analysis is performed on classified bitmap pattern information imported into a data sheet. Bitmap patterns may consist of single-bit failures, dual bits, rows, columns, or any complex pattern. A general instance of a failure is described internally preferably using a list of one or more bounding rectangles to specify the set of bits that failed. Each bounding rectangle is specified by the bit coordinates of the lower-left and upper-right corners of the rectangle.
Information on each of a die's bit failures can be viewed by toggling an “N of (total number of bit fails)” list in a Bit-Fail Browser. The following information may be displayed for each bit failure:    Array—the array where the bit failure occurred.    Block—the block where the bit failure occurred.    Pattern—the bit-fail pattern associated with the bit failure. If the bit failure is not associated with a defined bit-fail pattern, this field will be grayed out.    Bit Count—this field specifies the total number of bits that failed in the defined rectangle associated with the bit-fail pattern. The rectangle is defined by Array, Block, and logical coordinates (X0, Y0) and (X1, Y1).    Sub-Pattern—the index of the bounding rectangle(s) in the bit-fail pattern. Each sub-pattern has a range.    Range—the X0, X1, Y0, and Y1 coordinates describe the lower-left corner (X0, Y0) and the upper-right corner (X1, Y1) of the bounding rectangle associated with the current sub-pattern. These coordinates are in units of bits from the lower-left corner of the array/block.    Match—if this option is checked by a user, the bit failure has been matched to a known defect.    Reticle Repeater—if this option is checked by the user, the bit failure is repeating on the same reticle.
An enhanced Genesis™ Bitmap Analysis product module is also commercially available from the assignee of U.S. Pat. No. 6,470,229 B1 to extend the capabilities of the yield management system to direct bitmap-level analysis clustering. When defining a bit cluster pattern, a user has the following options: 1) selecting a radius specified by a number of “good” bits away from another failed bit before the current fail bit can be classified as part of the original bit cluster; 2) selecting a minimum count of failed bits in a bit cluster; and 3) selecting a maximum count of failed bits in a bit cluster. The bit clustering and aggregation system may then receive a defect data set. When a defect data set is received, the bit clustering and aggregation system starts with a failed bit and searches for neighboring failed bits. The bit clustering and aggregation system uses the specified radius to qualify the found failed bits to be part of the cluster or not. If the minimum count of failed bits is not met, the bit clustering and aggregation system will stop searching and move to the next failed bit. If the minimum count of failed bits is met, the bit clustering and aggregation system will continue to search for the next failed bit until it reaches the maximum fail bit count specified by the user. Aggregation is provided such that once clusters have been classified, the number of clusters that have the exact match or partial match to each other is counted.
In multi-level memory cell devices, each bit cell can contain more than two levels. With these additional levels, different failure mechanisms of the bit cell can now occur, which requires different analysis techniques to identify these failure mechanisms.
Thus, it would be desirable to provide a defect analysis system and method which overcome the above limitations and disadvantages of conventional systems and facilitate analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits leading to more effective quality control. It is to this end that the present invention is directed. The various embodiments of the system and method for analysis of multi-level memory in accordance with the present invention address the aforementioned problems and provide many advantages over conventional defect analysis systems and techniques.